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Low-k Dielectric Integration Cost Modeling

Published online by Cambridge University Press:  15 February 2011

Ed Korczynski
Ed Korczynski*
Affiliation:
Solid State Technology, 1700 S. Winchester Blvd., Suite 201, Campbell, CA 95008, Tel: 408–370–4833, Fax: 408–370–9585, [email protected]
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Abstract

The wide variety of low-k dielectric materials and processes for ULSI interconnection were sorted to create generic process flows. Average material and equipment costs were then used as inputs to a generic cost-per-wafer (CPW) model for dielectric deposition (not including the costs of dielectric CMP, metallization, or lithography). The model outputs are internally consistent, and useful for comparison of similar processes.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 476: Symposium N – Low-Dielectric Constant Materials III , 1997 , 177
Copyright
Copyright © Materials Research Society 1997

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References

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