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a-Si:H TFT: Potential Suitabilities for Gate and Source-Drain Self-Aligned Structure

Published online by Cambridge University Press:  21 February 2011

B. Diem  and
A. Chenevas-Paule
B. Diem
Affiliation:
LETI – Commissariat of l'Energie Atomique – 85 X – 38041 GRENOBLE CEDEX – France
A. Chenevas-Paule
Affiliation:
LETI – Commissariat of l'Energie Atomique – 85 X – 38041 GRENOBLE CEDEX – France
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Extract

Performances of a-Si:H TFT's are partly restricted by the parasitic capacitances due to the source-drain/gate overlapping and the channel length. These capacitances are inherent to the conventional photolithographic process [1] and to the MIS structure.

The use of the self-aligned a-Si:H TFT technology should allow the manufacture of short channel TFT's (L < 5 μm) where the overlapping length becomes negligible, on a large area as well as in high definition matrices. Such transistors could constitute in the near future the solution for high performances matrix arrays as well as their peripheral electronics.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 33: Symposium D – Comparison of Thin Film Transistor and SOI Technologies , 1984 , 281
Copyright
Copyright © Materials Research Society 1984

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References

REFERENCES

1. Machenzie, K.D. et al., Appl. Phys., A31, 87–92 (1983)Google Scholar
2. Meyer, S.E., RCA Review, 32, March 1971 Google Scholar
3. Asama, K. et al., SID'183 Digest, p. 144 Google Scholar
4. Sigiura, O. et al., Proc. Spring Meeting of Jap. Soc. Appl. Phys (1982 La S-6Google Scholar
5. Chenevas-Paule, A. and Diem, B., to be published.Google Scholar